High-Speed Event-Driven RTL Compiled Simulation

In this paper we present a new approach for generating high-speed optimized event-driven register transfer level (RTL) compiled simulators. The generation of the simulators is part of our BUILDABONG [7] framework, which aims at architecture and compiler co-generation for special purpose processors. The main focus of the paper is on the transformation of a given architecture’s circuit into a graph and applying on it an essential graph decomposition algorithm to transform the graph into subgraphs denoting the minimal subsets of sequential elements which have to be reevaluated during each simulation cycle. As a second optimization, we present a partitioning algorithm, which introduces intermediate registers to minimize the number of evaluations of combinational nodes during a simulation cycle. The simulator’s superior performance compared to an existing commercial simulator is shown. Finally, we demonstrate the pertinence of our approach by simulating a MIPS processor.